AMD Hiring for Smts Silicon Design Engineer (84826) at Hyderabad, Telangana, India Full Time

Job Description

What you do at AMD changes everything

At AMD, we push the boundaries of what is possible. We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center.

Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results. It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world. If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.
Requirements / Key Responsibilities:

• Responsible for participating in the pre-silicon verification for full chip, blocks, multi-chip andsystem-level verification
• Specifying design verification plan at soc level/IP level
• Specifying or reviewing verification plans for complex blocks within the ASIC
• Responsible for developing complex verification environment using the latest coverage/assertions based verification design methodology, which includes :self-checking, reusable, automated verification environment : both at full-chip & block level.Constrained random generators and reference models
• Carve out the scope and work hands-on on functional verification.
• Guide/mentor junior members on the team
• Work with internal/external stakholders to drive company-wide solutions

Job Requirements and Skills:

• B.E/B.Tech/M.E/M.Tech in Electrical/Electronics Engineering
• Minimum 13+ years of experience in ASIC Design Verification
• Must have excellent knowledge of ASIC Design Flow and SOC architecture
• Experience in developing complex testbench/model in verilog, System verilog or SystemC
• Experience with coverage-based verification methodology
• Experience in writing testplans and testcases
• Excellent debug skills in functional simulations are must.
• Experience in random test generation, coverage analysis, failure debug
• Experience in low power concepts/verification (NLP/UPF) and emulation is good-to-have
• Strong Verilog, SystemVerilog, PLI interface, C/C++, Perl/shell scripts programming skills.
• Must have very strong communication skills and the ability/desire to foster a team/global environment. EXP: 13 + Years

Location: Hyderabad
We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status. We will ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform essential job functions, and to receive other benefits and privileges of employment. Please contact us to request accommodation.
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13.00-16.00 Years