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ARM Hiring for Senior/Staff Digital Verification at Bangalore Full Time
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Job Purpose
What skills, experience, and qualifications do I need?
Job Description
We are the APD team, part of the Arm Physical Design Group. This diverse, engineering-centric group invents, defines, and develop innovative physical implementation methods for CPU/GPU class crafts using optimized physical IP. We pursue next-generation Arm CPUs and GPUs, inventing new concepts that will power billions of devices worldwide. To validate these new concepts (CPU cores, Interconnect, Memory, DAP..) on SoC testchips with success, we are looking for a hardworking Digital Verification engineer to join this outstanding team.
Job Requirements:
Job Purpose
As a Senior/Staff Digital Verification Engineer, you will Support and own the Verification on multiple types of projects especially on SoC testchips and apply innovative verification techniques to validate new CPU, GPU and digital IPs at RTL and gate level. You will be also involved in the Design team to fix and/or develop RTL design. You will be able to run synthesis and have basics to setup constraints. You are familiar with DFT concepts and able to run ATPG, knowledge on MBIST insertion would be appreciated.
In this role, we expect a proactive and autonomous candidate to provide and specify the verification plans to validate all features and stress the design in corner cases to find all possible bugs!
Responsibilities include
- Understanding the specification of the SoC you will target.
- Defining test plan, creating verification environment. Reporting bugs to design team; plus specifying the verification sign-off criteria.
- Building the testbench by using appropriate methodology and programming language(s).
- Running tests to stress the design in its last corner cases and find all possible bugs
- Delivering patterns to Silicon Validation team and providing debug support during silicon bring-up.
What skills, experience, and qualifications do I need?
- 5+ Years of work experience of relevant SoC and IP level verification.
- Excellent Knowledge in Verilog coding and debugging skills.
- Experience of RTL simulations and Gate simulations using Back-annotation.
- Good knowledge in C and C++ (or System Verilog) programming skills, and strong low-level programming skills in assembly and/or low-level C
- Highly motivated to “break” the design and find bugs, and have a reasonable appreciation of the verification methodology linked to this activity
- Good knowledge with validation at SOC and IP level
- Good knowledge with Verilog and system Verilog for testbench (rtl, gate level and power aware simulation) UVM methodology
- Experience of RTL coding with Verilog and system Verilog
- Knowledge of DFT and experience with ATPG
- Good knowledge on AMBA bus architecture (AXI, AHB, APB)
- Exposed to the RTL hardware design flow and methodology
- General understanding of semiconductor IP development threads and challenges
Educational Qualifications
BE/B. Tech or MS/M. Tech
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