Intel Hiring for Layout Verification Engineer at Bengaluru, Karnataka, India Full Time

Job Description

About IFS
As an integral part of Intel’s new IDM2.0 strategy, we are establishing Intel Foundry Services (IFS), a fully vertical, standalone foundry business, reporting directly to the CEO. IFS will be a world-class foundry business and major provider of US and European-based capacity to serve customers globally. Intel Foundry Services will be differentiated from other Foundry offerings with a combination of leading-edge packaging and process technology, committed capacity in the US and Europe – available for customers globally – and a world-class IP portfolio that customers can chose from including x86 cores, graphics, media, display, AI, interconnect, fabric and other critical foundational IP, along with ARM and RISC-V ecosystem IPs. IFS will also provide access to silicon design services to help our customers seamlessly turn silicon into solutions, using industry standard design packages. This business unit is completely dedicated to the success of its customers with full P and L responsibilities. This model will ensure that our foundry customers’ products will receive our utmost focus in terms of service, technology enablement and capacity commitments. IFS is already engaged with customers today starting with our existing foundry offerings and we are expanding imminently to include our most advanced technologies, which are optimized for cutting-edge performance, making them ideal for high-performance applications. We are looking for expert engineers to work on layout integration, convergence and signoff of IFS design tapeouts. The responsibilities includes but not limited to- Integration and generation of layout and netlist views of different levels of hierarchy up to SoC. – Layout verification and signoff for IP blocks, APR partition and SoC levels of hierarchy. – Develop Tcl and Perl script automations to efficiently implement layout edits in APR designs. – Develop plans and implement audit of incoming layouts, thereby set minimum acceptable criteria. – Provide timely feedback to design teams on layout quality throughout design phase of a project. – Liaison with PDK, Tools, flow and Methodology teams along with other stakeholders to pre-empt issues and to be abreast of latest changes in foundry rules.Right Candidate will bring-in 5+ years of technical experience in the layout integration, netlisting, layout clean-up, verification and final tapeout activities on high-end SOCs such as Server CPUs/SOCs, Graphics SOCs or SOCs in AI Space on 10nm, 7nm or 5nm or other advanced foundry processes. The candidate must be an good problem solver and with agile/fast moving mindset and customer oriented. Proactive attitude to build a correct by construction layout techniques, planned and organized work style and excellent team work needed.
Qualifications

Bachelors/Masters degree in Electronics/Computer Science required with 5+ year’s experience Inside this Business Group
As the world’s largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art – from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth
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