Design and Development of HDL Friendly Simulink Blocks
Understand and Implement Mathematical Algorithms for HDL Code Generation
Contribution to Floating and Fixed Point Algorithms
Optimized Generation of HDL Code from Simulink Blocks
Timing and Area Optimization for HDL Blocks
Developement Code Review and Documentation
Expertise in VHDL or Verilog
Expertise in C or C++
Knowledge of Front End Tools such as Xilinx Vivado, Intel Quartus etc
Knowledge of Scripting Langugaes such perl or tcl
Knowledge of Simulation Tools such as ModelSim, QuestaSim
Knowledge of FPGA/ASIC Development Cycle
Knowledge of MATLAB/Simulink/HDL Coder is a plus
A bachelor’s degree and 7 years of professional work experience (or a master’s degree and 5 years of professional work experience, or a PhD degree, or equivalent experience) is required.
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