Verification engineer – Bengaluru – Sventl Asia Pacific Full Time

Description

Job Description:

SVENTL India Pvt. Ltd. is looking for talented and experienced Verification Engineers to join our dynamic team for multiple ongoing and upcoming projects across India and Southeast Asia. If you are passionate about IP/SoC verification and eager to work on challenging, cutting-edge designs using SystemVerilog and UVM, we invite you to be a part of our growing organization.

Key Responsibilities:

• Perform functional verification of IP or SoC-level designs using SystemVerilog and UVM methodologies
• Develop and maintain verification plans, testbenches, test cases, and coverage metrics
• Collaborate closely with design, architecture, and validation teams
• Debug RTL and testbench issues and work towards timely resolution
• Contribute to automation and continuous improvement of verification processes

Required Skills:

• 3 to 9 years of hands-on experience in SystemVerilog and UVM-based verification
• Strong understanding of IP/SoC-level verification techniques
• Solid debugging skills and familiarity with simulation tools (e.g., VCS, Questa, Incisive)
• Experience with scripting languages (e.g., Python, Perl, Shell) is a plus
• Good communication and teamwork skills