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Western Digital Hiring for System Verilog/UVM verification Engineer at Bengaluru, India Full Time
- Study and understand the Design Specification documents and come up with test plan. * Testing various features at full-chip as well as module-level using targetted/random/corner-case/coverage tests. * Hands-on contributions to SVA development like coding, porting and maintaining System Verilog Assertions * Run regressions and extract Code/Functional Coverage. * Debug failures and root-cause it by interacting with other teams/groups Etc. Verification closure using Functional/Code Coverage analysis * Hands-on contributions to SVA development like coding, porting and maintaining System Verilog Assertions * Test Plan development for verification closure using SVA * Testing various features at full-chip as well as module-level using targetted/random/corner-case/coverage tests, * Run regressions and extract Code/Functional Coverage, * Debug failures and root-cause it by interacting with other teams/groups Etc.