Xilinx Hiring for Senior Design Engineer at Hyderabad, Telangana, India Full Time

Job Description

Description Xilinx is now part of Advanced Micro Devices (AMD).

At AMD, we push the boundaries of what is possible. We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies ‘ building blocks for gaming, immersive platforms, and the data center.

Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the ‘extra mile’ to achieve unthinkable results. It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world. If you have this type of passion, we invite you to take a look at the opportunities available to come join our team. AMD is looking for a talented individual to join the high speed memory interfaces design engineering group, in the position of Senior Design Engineer to work on the modelling of next generation memory controllers and network on a chip bus. The successful candidate will work as a contributing member responsible for the architecture and design of next generation memory controller models for Xilinx customers. Responsibilities include System Verilog/System C coding, architecting, implementing, documenting and validating the models. The area of focus would be on controllers like DDR4, DDR5, LPDDR4, LPDDR5 & HBM. The candidate must have excellent inter-personal and communication skills and be able to work independently. Xilinx holds a strong position in the FPGA all programmable paradigm. This position offers candidates exposure to the latest generation IP, tools, boards, FPGA products and the ability to design and develop high speed memory IP cores.

• B.E/M.E/M.Tech or B.S/M.S in EE/CE with 9+ years of experience in BFM modeling and functional verification
• Experience in developing System-Verilog based verification environment using industry standard methodologies like OVM/UVM
• Expertise in behavioral modelling of the functional blocks using System-Verilog & SystemC
• Experience in AXI bus or NOC bus based multi-master & slave systems
• Knowledge of DRAM memory controllers and user traffic patterns for bandwidth & latency analysis
• Strong working knowledge of UNIX environment and scripting languages such as Perl, Tcl & Python
• Good waveform debug skills using front end industry standard design tools like VCS, NCSIM, Verdi and ModelSim
• Excellent communication and problem solving skills