Xilinx India Technology Services Pvt Ltd Hiring for Rtl Design Engineer 2 at Hyderabad/ Secunderabad (Andhra Pradesh), Full Time

Job Description

Xilinx is looking for a talented individual to join the high speed memory interfaces design engineering group, in the position of Design Engineer-1 to work on development of next generation highly configurable blocks that operate at over 1 GHz data rate.

The successful candidate will own IP packaging and verification of complex blocks to meet configuration requirements. The area of focus will be on development of IP framework, providing flexible configuration options during IP packaging, integration, Vivado synthesis/implementation constraint development, interaction with RTL/SoC architecture team, and IP quality checks.

Xilinx holds a strong position in the FPGA all programmable paradigm. This position offers candidates exposure to the latest generation IP, tools, boards, FPGA products and the ability to design and develop high speed memory IP cores.

B.E/M.E/M.Tech or B.S/M.S in EE/CE with 2 years of relevant experience
Excellent Verilog and logic design concepts
Experience with Xilinx Vivado tool
Experience with automation using scripting techniques such as PERL, Python or TCL
Knowledge of bus protocols like AXI/AHB
Excellent waveform debug skills using front end industry standard design tools like VCS, NCSIM, and ModelSim.
Excellent communication and problem solving skills.
Should have experience working in geographically dispersed team and should be a strong team player
Education: Any Graduate
Industry: Software Services, IT-Software

Skills Required