Intel Technologies

Job Description

Platform Validation Architect
Creates, defines and develops FV – functional validation and System validation environment and test suites. Uses and applies tools and techniques to ensure solution and system level use cases and features along with functional, System, Stress and performance requirements are validated. Responsible for the development of methodologies, execution of validation plans, and debug of failures. Requires broad understanding of multiple system areas and requires interfaces with Architecture, Design, and Pre-silicon Validation teams in improving post-silicon test content and providing feedback
We are looking for engineers who bring fresh ideas from areas including Intel Platforms, Memory Subsystem, Storage and Security. We need our engineers to be versatile, display leadership qualities and be eager to take on new problems across the platform as we continue to push technology forward.
Responsibilities:
Drive test efforts from planning and development to execution and delivery.
Participate in developing effective test strategies for DCPMM validation at functional, feature, system, stress, reliability and security level
Design and develop reliable, scalable test automation using PythonSV / Python to validate product features in data availability, Manageability, Synthetic and Customer Workloads, Stress, Stability, Reliability and Security areas
Diagnose debug and perform root cause analysis of DCPMM, Memory Subsystem, Platform level and management tools related issues
Work with Intel CPU and IP teams for test case design and issue debug

Qualifications

B.Tech or M.Tech in Computer Science, Electrical Engineering or similar degree with 5 years of relevant experience with:
A track record of successful FV validation experience with exposure to Intel IPs and platforms, good to have – exposure to Memory subsystem.
Validation expertise and experience in the following technologies
o FV, SVOS, Memicals – Memory Traffic Generator from SVOS, SuperCollider etc..
o Server Architecture knowledge
o Server Memory architecture
o Memory training
o System Architecture – HW-FW-SW as a whole.
o SVOS based validation and debug experience
Experience in Post-Si validation
Strong knowledge of Python, Perl, test automation frameworks
Good knowledge of test strategies and use cases for validating Data center platforms with focus on CPU and Memory subsystems
Education: Any Graduate
Industry: Telecom, IT-Hardware/Networking