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Seagate Technology Hiring For Intern – VLSI DV at Pune, Maharashtra Full Time
About our group:
The group is part of Seagate’s VLSI Organization spread globally across multiple sites. Seagate designs world class controller SoCs for their HDDs. The group in Pune participates in design, verification, physical design and post-silicon validation activities of these complex SoCs. This group has some of the best talent from the industry and has taped out many controller chips.
The group is part of Seagate’s VLSI Organization spread globally across multiple sites. Seagate designs world class controller SoCs for their HDDs. The group in Pune participates in design, verification, physical design and post-silicon validation activities of these complex SoCs. This group has some of the best talent from the industry and has taped out many controller chips.
About the role – you will:
Receive training on Functional Verification Methodologies at IP and SoC level using SystemVerilog and UVM. After due training you will be able to work on verifying designs using Synopsys Simulation tools.
Develop Test-bench & Reference models in IP & SoC level verification environments.
Document and Implement Verification Plans.
Work closely with design engineers to create constrained random based test-benches and test cases to meet the required functional and code coverage metrics.
Debug and help resolve test failures.
Create reusable verification environments to be used across multiple teams.
Complete internship project as per plan.
About you:
Knowledge of ASIC design flow and tools.
Good understanding of Circuit design, Logic design, Setup time, Hold time, Combinatorial and Sequential circuits, CMOS and Power consumption.
Self-motivated & a strong team player.
Strong debug and analytical skills.
Ability to quickly learn new tools and technologies.
Your experience includes:
Verilog, SystemVerilog, VHDL, UVM or other verification methodologies.
C++ or other OOP languages with strong background in OOP concepts.
Perl, Tcl, Shell or other scripting languages.
VLSI engineering cycle.
Location:
Location: Pune, India